(1) Field of the Invention
The present invention relates to the field of computer systems architecture. More specifically, the present invention relates to Direct Memory Access (DMA) controllers.
(2) Description of Related Art
DMA controllers are used in computer systems for moving blocks of data from one location to another location, while relieving the host processor of the need to generate a long sequence of addresses to accomplish the transfer of data. Typically, the data transferred is a large block of data which begins at a source address and is moved to a destination beginning at a destination address. The DMA controller is started by an event responsive to which the DMA controller generates addresses of a source location and of a destination location wherein data is transferred.
In many storage devices such as memories, data can be stored on double-word boundaries, each double-word consisting of four bytes of data. In such memories, each read or write cycle, from or to the memory, involves accessing a double-word from either the source or the destination memory. Data, however, may be stored on boundaries other than double-word such as byte or word boundaries. However, a DMA transfer of a block of data between a source storage device and a destination storage device becomes more complicated when the starting address in the source storage device does not align on byte boundaries with the starting address in the destination storage device.
FIG. 1 shows a source storage device 2 storing a block of twelve bytes of data starting at address 000 0201H. This address corresponds to the address of the first byte of data of the block of twelve bytes stored in the source storage device 2. The first byte of data of the block resides at the second byte location of the double word having the address 000 0200H. The block of data from the source storage device is received by the destination storage device 4 which stores this block beginning with the fourth byte of data of the double word having the address 4001 0300H. According to this configuration, a DMA controller would have to read bytes B.sub.1, B.sub.2, and B.sub.3 of the first double word starting at address 000 0200H. Then, bytes B.sub.1, B.sub.2, and B.sub.3 would be written in one cycle to a temporary storage device. The DMA controller would then, in another cycle, write byte B.sub.1 in the destination storage device at address 4001 0303H. A second read operation from the source storage device would retrieve the double word starting at address 000 0204H. Bytes B.sub.4 and B.sub.5 would thus have to be stored in, the temporary storage device together, with bytes B.sub.2 and B.sub.3 aligned in the sequence B.sub.5 B.sub.4 B.sub.3 B.sub.2. However, bytes B.sub.6 and B.sub.7 together with B.sub.5 and B.sub.4 from address 000 0204H would have to be read again from the source storage device in a next cycle because the temporary storage device would be full with the double-word B.sub.5 B.sub.4 B.sub.3 B.sub.2. As one can see, the discrepancy in alignment between the configuration of the block of data stored in the source storage device 2 and the configuration of data to be stored in the destination storage device 4 causes an additional read cycle penalty (i.e., reading from the source storage device the double word including the sequence B.sub.5 B.sub.4 B.sub.3 B.sub.2).
It is desirable to provide a faster and more efficient mechanism for aligning data transferred from a source storage device 2 into a destination storage device 4 on byte, word, and double word boundaries. This is particularly critical in applications requiring transfer of blocks of data at high speed.
DMA controllers can be particularly useful in conjunction with a Peripheral Component Interconnect (PCI) system. Integration of a DMA controller into a PCI system, however, may require compliance with PCI protocols for transfer of data. For example, in a PCI system, according to the revision 7.1 of the PCI Special Interest Group located in Portland, Oreg., local memory to PCI transfers can be performed by means of two PCI write commands: Memory Write (MW), and Memory Write and Invalidate (MWI). The Memory Write (MW) can be used by a computer system in which a DMA controller is integrated to write data to a PCI agent. The Memory Write command is a command compatible with the PCI system architecture which is used to update data in the memory. A Memory Write and Invalidate (MWI) command is semantically similar to the Memory Write command except that it additionally guarantees a minimum transfer of one complete cacheline during the current transaction. According to this command, the master intends to write all bytes within an address cacheline in a single PCI transaction unless the master is interrupted by the target. This command allows a memory performance optimization by invalidating a dirty line in a write-back cache without requiring the actual write-back cycle, thus shortening access time. If the target, i.e., the PCI agent is cacheable memory, the Memory Write and Invalidate (MWI) command improves the system performance. For more information about the PCI systems and the Memory Write and Invalidate command, see The PCI Local Bus Specification, revision 2.1 of the PCI Special Interest Group, located in Portland, Oreg.
In order to use the Memory Write and Memory Write and Invalidate commands on the PCI bus when a DMA transfer between local memory and PCI bus is desired, a DMA channel has to be programmed by the application software. However, there are a number of circumstances which may prevent a DMA controller from actually initiating the MWI command. For example, to satisfy the PCI requirements for MWI, the PCI master such as a DMA controller would have to start a transaction on a cacheline boundary and transfer at least one cacheline of data without interruption. The application software would need to be responsible for compliance with the PCI requirements.
Observance of the PCI requirements by the application software, however, poses significant overhead problems. The software would first have to be fairly complicated, and the system performance would be affected by the use of the respective software design. A hardware mechanism, providing full PCI compliance for a DMA controller transferring data between a local and a PCI bus would be advantageous over software implementation. It is, thus, desirable to provide for a hardware apparatus for implementing MWI and MW transfers of data on a DMA controller for transferring data between a local and a PCI bus.
Additionally, the implementation of a DMA controller in conjunction with a PCI system may be confronted with significant problems when errors on the local bus need to be handled. For example, if a local bus error occurs after a PCI retry is received from a slave circuit, the DMA controller may not be able to terminate the transfer. A retry request, in PCI compliant systems, is typically generated by a slave circuit to a master circuit, such as a DMA controller if the slave is unable to respond to a transaction at a current time. According to PCI revision 2.1, the DMA controller would first need to service the retry request. Otherwise, if the retry is not serviced, the PCI slave could lock up.
An example of the need for a retry in PCI systems would be if the slave is currently locked for exclusive access by another master. The occurrence of a local bus error followed by a PCI retry poses the following problem. In order to avoid transferring data, which might contain errors, from the local bus to the PCI bus, it would be desirable to end the transfer when the error signal from the local bus is received. However, a transfer cannot be terminated until the retry is satisfied. In order to satisfy the retry, the DMA controller needs to prevent the host processor from noticing that an error has occurred. If the DMA controller did not convey the host processor the error message and serviced the retry from the slave which initially generated the retry signal, the host processor would retain ownership over the PCI bus and, thus, the transfer of the block of data programmed to be transferred in a DMA transfer would continue. Continuing the transfer of data after having received an error message would, however, require sophisticated error handling logic circuit. Such error handling logic circuit would be expensive due to the complexity of this circuit.
It is, thus, desirable to provide a DMA error handling logic capable of handling with minimum overhead a local bus error after a PCI retry request. It is also desirable to provide a mechanism capable of servicing a pending retry and aborting the DMA transfer in course, once the retry was serviced, without the need to substantially change the design of the error handling logic.